tf.vhd
--
-- T-F.F. with asynchronous reset
--
library ieee;
use ieee.std_logic_1164.all;
entity tf is
port( t : in std_logic;
nr : in std_logic;
q : out std_logic);
end tf;
architecture rtl of tf is
signal bufQ : std_logic;
begin
process(nr,t)
begin
if (nr = '0') then
bufQ <= '0';
elsif (t'event and t = '1') then
bufQ <= not bufQ;
end if;
end process;
q <= bufQ;
end rtl;