sr4pe.vhd
--
-- 4-bit shift-reg. with asynchronous parallel preset & enable
--
library ieee;
use ieee.std_logic_1164.all;
entity sr4pe is
port( d : in std_logic_vector(3 downto 0); -- parallel preset data
p : in std_logic; -- asynchronous paralell preset
si : in std_logic; -- serial input data
e : in std_logic; -- shift enable
c : in std_logic;
nr : in std_logic;
q : out std_logic_vector(3 downto 0) );
end sr4pe;
architecture rtl of sr4pe is
signal bufQ : std_logic_vector(3 downto 0);
begin
process(nr,p,d,c)
begin
if (nr = '0') then
bufQ <= (others => '0');
elsif (p = '1') then
bufQ <= d;
elsif (c'event and c = '1') then
if (e = '1') then
bufQ <= bufQ(2 downto 0) & si;
end if;
end if;
end process;
q <= bufQ;
end rtl;