sr4_bidir.vhd
--
-- synchronous bidirectional 4-bit shift-reg.
--
-- *** control signal table ***********
--
-- ctrl1 ctrl0 function
-- 1 1 load parallel data
-- 1 0 shift left
-- 0 1 shift right
-- 0 0 hold
--
-- ************************************
library ieee;
use ieee.std_logic_1164.all;
entity sr4_bidir is
port( d : in std_logic_vector(3 downto 0); -- parallel load data
sir : in std_logic; -- serial input for right-shift
sil : in std_logic; -- serial input for left-shift
ctrl : in std_logic_vector(1 downto 0); -- control
c : in std_logic;
nr : in std_logic;
q : out std_logic_vector(3 downto 0) );
end sr4_bidir;
architecture rtl of sr4_bidir is
signal bufQ : std_logic_vector(3 downto 0);
begin
process(nr,c)
begin
if (nr = '0') then
bufQ <= (others => '0');
elsif (c'event and c = '1') then
if (ctrl = "11") then
bufQ <= d;
elsif (ctrl = "10") then
bufQ <= bufQ(2 downto 0) & sil;
elsif (ctrl = "01") then
bufQ <= sir & bufQ(3 downto 1);
end if;
end if;
end process;
q <= bufQ;
end rtl;