sr4.vhd


--
-- D-F.F. with asynchronous reset
--

library ieee;
use ieee.std_logic_1164.all;

entity df is
     port( d : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         q : out std_logic);
end df;

architecture rtl of df is
begin

     process(nr,c)
     begin

         if (nr = '0') then
             q <= '0';
         elsif (c'event and c = '1') then
             q <= d;
         end if;

     end process;

end rtl;

--
-- 4-bit shift-reg.
--

library ieee;
use ieee.std_logic_1164.all;

entity sr4 is
     port( d : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         q : out std_logic_vector(3 downto 0) );
end sr4;

architecture rtl of sr4 is

component df
     port( d : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         q : out std_logic);
     end component;

     signal bufQ : std_logic_vector(3 downto 0);

begin

     mod0 : df port map(
          d => d,
          c => c,
          nr => nr,
          q => bufQ(0) );

     mod1 : df port map(
          d => bufQ(0),
          c => c,
          nr => nr,
          q => bufQ(1) );

     mod2 : df port map(
          d => bufQ(1),
          c => c,
          nr => nr,
          q => bufQ(2) );

     mod3 : df port map(
          d => bufQ(2),
          c => c,
          nr => nr,
          q => bufQ(3) );

          q <= bufQ;

end rtl;