sqWaitB.vhd


--
-- decrement library
--

library ieee;
use ieee.std_logic_1164.all;

package libDec is
      function decrement4(sorce : std_logic_vector(3 downto 0)) return std_logic_vector;
end libDec;

package body libDec is
      function decrement4(sorce : std_logic_vector(3 downto 0)) return std_logic_vector is
           variable orAll : std_logic;
           variable temp : std_logic_vector(sorce'high downto sorce'low);
      begin
           orAll := '0';
           for j in sorce'low to sorce'high loop
                temp(j) := sorce(j) xor (not orAll);
                orAll := orAll or sorce(j);
           end loop;
           return(temp);
      end decrement4;
end libDec;

--
-- sequencer include timer controled wait state
--

library ieee;
use ieee.std_logic_1164.all;
use work.libDec.all;

entity sqWaitB is
     port( start : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         st1 : out std_logic;
         st2 : out std_logic;
         st3 : out std_logic;
         st4 : out std_logic;
         st5 : out std_logic;
         monitTimer : out std_logic_vector(3 downto 0) );
end sqWaitB;

architecture rtl of sqWaitB is

     signal nonState : std_logic;
     signal st1In : std_logic;
     signal st3In : std_logic;
     signal st4In : std_logic;
     signal stBuf : std_logic_vector(5 downto 1);

     signal timer : std_logic_vector(3 downto 0);
     signal timerZero : std_logic;

begin

     process(nr,c)
     begin

           if (nr = '0') then
                stBuf <= (others => '0');
                timer <= (others => '0');
           elsif (c'event and c = '1') then
                stBuf(2 downto 1) <= stBuf(1) & st1In;
                stBuf(3) <= st3In;
                stBuf(5 downto 4) <= stBuf(4) & st4In;

                if (stBuf(2) = '1') then
                      timer <= "1001";
                elsif (timerZero = '0') then
                      timer <= decrement4(timer);
                end if;
           end if;

    end process;

-- start
    nonState <= '1' when (stBuf = "00000") else '0';
    st1In <= nonState and start;
-- wait loop
    st3In <= stBuf(2) or (stBuf(3) and (not timerZero) );
-- loop out
    st4In <= stBuf(3) and timerZero;

    timerZero <= '1' when (timer = "0000") else '0';

    st1 <= stBuf(1);
    st2 <= stBuf(2);
    st3 <= stBuf(3);
    st4 <= stBuf(4);
    st5 <= stBuf(5);

    monitTimer <= timer;

end rtl;