sqLoopA.vhd


--
-- sequencer include loop control
--

library ieee;
use ieee.std_logic_1164.all;

entity sqLoopA is
     port( start : in std_logic;
         ctrl : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         st1 : out std_logic;
         st2 : out std_logic;
         st3 : out std_logic;
         st4 : out std_logic;
         st5 : out std_logic;
         st6 : out std_logic;
         st7 : out std_logic);
end sqLoopA;

architecture rtl of sqLoopA is

     signal nonState : std_logic;
     signal st1In : std_logic;
     signal st3In : std_logic;
     signal st7In : std_logic;
     signal stBuf : std_logic_vector(7 downto 1);

begin

     process(nr,c)
     begin

           if (nr = '0') then
                stBuf <= (others => '0');
           elsif (c'event and c = '1') then
                stBuf(2 downto 1) <= stBuf(1) & st1In;
                stBuf(6 downto 3) <= stBuf(5 downto 3) & st3In;
                stBuf(7) <= st7In;
           end if;

     end process;

-- start
     nonState <= '1' when (stBuf = "0000000") else '0';
     st1In <= nonState and start;
-- wait loop
     st3In <= stBuf(2) or (stBuf(6) and (not ctrl) );
-- loop out
     st7In <= stBuf(6) and ctrl;

     st1 <= stBuf(1);
     st2 <= stBuf(2);
     st3 <= stBuf(3);
     st4 <= stBuf(4);
     st5 <= stBuf(5);
     st6 <= stBuf(6);
     st7 <= stBuf(7);

end rtl;