sel4_A.vhd
--
-- 4-to-1 data selector (use with-select statement)
--
library ieee;
use ieee.std_logic_1164.all;
entity sel4_A is
port( dD : in std_logic;
dC : in std_logic;
dB : in std_logic;
dA : in std_logic;
sel : in std_logic_vector(1 downto 0);
y : out std_logic);
end sel4_A;
architecture rtl of sel4_A is
begin
with sel select
y <= dD when "11",
dC when "10",
dB when "01",
dA when others;
end rtl;