pEnc2.vhd
--
-- 4-to-2 priority encoder
--
library ieee;
use ieee.std_logic_1164.all;
entity pEnc2 is
port( a3 : in std_logic;
a2 : in std_logic;
a1 : in std_logic;
a0 : in std_logic;
y : out std_logic_vector(1 downto 0) );
end pEnc2;
architecture rtl of pEnc2 is
begin
y <= "11" when (a3 = '1') else
"10" when (a2 = '1') else
"01" when (a1 = '1') else
"00";
end rtl;