jkf_A.vhd


--
-- JK-F.F. (use logical equation)
--

library ieee;
use ieee.std_logic_1164.all;

entity jkf_A is
     port( j : in std_logic;
         k : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         q : out std_logic);
end jkf_A;

architecture rtl of jkf_A is

     signal bufQ : std_logic;

begin

     process(nr,c)
     begin

           if (nr = '0') then
               bufQ <= '0';
           elsif (c'event and c = '1') then
               bufQ <= (j and (not bufQ) ) or (k nor (not bufQ) );
           end if;

     end process;

     q <= bufQ;

end rtl;