inc5_func.vhd


--
-- increment library
--

library ieee;
use ieee.std_logic_1164.all;
package libInc is
      function increment5(source : std_logic_vector(4 downto 0)) return std_logic_vector;
end libInc;

package body libInc is
      function increment5(source : std_logic_vector(4 downto 0)) return std_logic_vector is
           variable andAll : std_logic;
           variable temp : std_logic_vector(source'high downto source'low);
      begin
           andAll := '1';
           for j in source'low to source'high loop
                temp(j) := source(j) xor andAll;
                andAll := andAll and source(j);
           end loop;
           return(temp);
      end increment5;
end libInc;

--
-- 5-bit incrementor (use function)
--

library ieee;
use ieee.std_logic_1164.all;
use work.libInc.all;

entity inc5_func is
     port( a : in std_logic_vector(4 downto 0);
         y : out std_logic_vector(4 downto 0) );
end inc5_func;

architecture rtl of inc5_func is
begin

     y <= increment5(a);

end rtl;