faT.vhd


--
-- full adder from truth table
--
library ieee;
use ieee.std_logic_1164.all;

entity faT is
     port(   a : in std_logic;
           b : in std_logic;
           ci : in std_logic;
           co : out std_logic;
           s : out std_logic);
end faT;

architecture rtl of faT is

     signal tableIn : std_logic_vector(2 downto 0);
     signal tableOut : std_logic_vector(1 downto 0);

begin

     tableIn <= b &; a & ci;

     with tableIn select
          tableOut <= "11" when "111",
                  "10" when "110",
                  "10" when "101",
                  "01" when "100",
                  "10" when "011",
                  "01" when "010",
                  "01" when "001",
                  "00" when others;

      co <= tableOut(1);
      s <= tableOut(0);

end rtl;