dfe8.vhd


--
-- 8-bit D-reg. with synchronous enable
--

library ieee;
use ieee.std_logic_1164.all;

entity dfe8 is
     port( d : in std_logic_vector(7 downto 0);
         e : in std_logic;
         c : in std_logic;
         nr : in std_logic;
         q : out std_logic_vector(7 downto 0));
end dfe8;

architecture rtl of dfe8 is
begin

     process(nr,c)
     begin

           if (nr = '0') then
               q <= (others => '0');
           elsif (c'event and c = '1') then
                if (e = '1') then
                    q <= d;
                end if;
           end if;

     end process;

end rtl;