dec3_B.vhd
--
-- 3-to-8 decoder (use when-else statement)
--
library ieee;
use ieee.std_logic_1164.all;
entity dec3_B is
port( a : in std_logic_vector(2 downto 0);
e : in std_logic;
y7 : out std_logic;
y6 : out std_logic;
y5 : out std_logic;
y4 : out std_logic;
y3 : out std_logic;
y2 : out std_logic;
y1 : out std_logic;
y0 : out std_logic);
end dec3_B;
architecture rtl of dec3_B is
signal inBuf : std_logic_vector(3 downto 0);
begin
inBuf <= e & a;
y7 <= '1' when (inBuf = "1111") else '0';
y6 <= '1' when (inBuf = "1110") else '0';
y5 <= '1' when (inBuf = "1101") else '0';
y4 <= '1' when (inBuf = "1100") else '0';
y3 <= '1' when (inBuf = "1011") else '0';
y2 <= '1' when (inBuf = "1010") else '0';
y1 <= '1' when (inBuf = "1001") else '0';
y0 <= '1' when (inBuf = "1000") else '0';
end rtl;