dec3_A.vhd


--
-- 3-to-8 decoder (use logical equation)
--

library ieee;
use ieee.std_logic_1164.all;

entity dec3_A is
     port( a : in std_logic_vector(2 downto 0);
         e : in std_logic;
         y7 : out std_logic;
         y6 : out std_logic;
         y5 : out std_logic;
         y4 : out std_logic;
         y3 : out std_logic;
         y2 : out std_logic;
         y1 : out std_logic;
         y0 : out std_logic);
end dec3_A;

architecture rtl of dec3_A is

begin

    y7 <= e and a(2) and a(1) and a(0);
    y6 <= e and a(2) and a(1) and (not a(0));
    y5 <= e and a(2) and (not a(1)) and a(0);
    y4 <= e and a(2) and (not a(1)) and (not a(0));
    y3 <= e and (not a(2)) and a(1) and a(0);
    y2 <= e and (not a(2)) and a(1) and (not a(0));
    y1 <= e and (not a(2)) and (not a(1)) and a(0);
    y0 <= e and (not a(2)) and (not a(1)) and (not a(0));

end rtl;