count5_func.vhd


--
-- increment library
--

library ieee;
use ieee.std_logic_1164.all;
package libInc is
      function increment5(source : std_logic_vector(4 downto 0)) return std_logic_vector;
end libInc;

package body libInc is
      function increment5(source : std_logic_vector(4 downto 0)) return std_logic_vector is
           variable andAll : std_logic;
           variable temp : std_logic_vector(source'high downto source'low);
      begin
           andAll := '1';
           for j in source'low to source'high loop
                temp(j) := source(j) xor andAll;
                andAll := andAll and source(j);
           end loop;
           return(temp);
      end increment5;
end libInc;

--
-- 5-bit counter (use function)
--

library ieee;
use ieee.std_logic_1164.all;
use work.libInc.all;

entity count5_func is
     port( c : in std_logic;
         nr : in std_logic;
         q : out std_logic_vector(4 downto 0) );
end count5_func;

architecture rtl of count5_func is

     signal bufQ : std_logic_vector(4 downto 0);

begin
     process(nr,c)
     begin
           if (nr = '0') then
                bufQ <= (others => '0');
           elsif (c'event and c = '1') then
                bufQ <= increment5(bufQ);
           end if;
     end process;

     q <= bufQ;

end rtl;