adder5lf.vhd


--
-- 5-bit adder (use for-generate loop / logical equation)
--

library ieee;
use ieee.std_logic_1164.all;

entity adder5lf is
     port( a : in std_logic_vector(4 downto 0);
         b : in std_logic_vector(4 downto 0);
         ci : in std_logic;
         co : out std_logic;
         s : out std_logic_vector(4 downto 0) );
end adder5lf;

architecture rtl of adder5lf is

     signal interCarry : std_logic_vector(4 downto 1);

begin

     co <= (a(4) and b(4) ) or ( (a(4) or b(4) ) and interCarry(4) );
     s(4) <= a(4) xor b(4) xor interCarry(4);

     gen : for j in 3 downto 1 generate
          interCarry(j + 1) <= (a(j) and b(j) ) or ( (a(j) or b(j) ) and interCarry(j) );
          s(j) <= a(j) xor b(j) xor interCarry(j);
     end generate;

     interCarry(1) <= (a(0) and b(0) ) or ( (a(0) or b(0) ) and ci);
     s(0) <= a(0) xor b(0) xor ci;

end rtl;