adder3.vhd
--
-- full adder
--
library ieee;
use ieee.std_logic_1164.all;
entity fa is
port( a : in std_logic;
b : in std_logic;
ci : in std_logic;
co : out std_logic;
s : out std_logic);
end fa;
architecture rtl of fa is
begin
co <= (a and b) or ( (a or b) and ci);
s <= a xor b xor ci;
end rtl;
--
-- 3-bit adder
--
library ieee;
use ieee.std_logic_1164.all;
entity adder3 is
port( a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0);
ci : in std_logic;
co : out std_logic;
s : out std_logic_vector(2 downto 0) );
end adder3;
architecture rtl of adder3 is
component fa
port( a : in std_logic;
b : in std_logic;
ci : in std_logic;
co : out std_logic;
s : out std_logic);
end component;
signal interCarry : std_logic_vector(2 downto 1);
begin
mod2 : fa port map(
a => a(2),
b => b(2),
ci => interCarry(2),
co => co,
s => s(2) );
mod1 : fa port map(
a => a(1),
b => b(1),
ci => interCarry(1),
co => interCarry(2),
s => s(1) );
mod0 : fa port map(
a => a(0),
b => b(0),
ci => ci,
co => interCarry(1),
s => s(0) );
end rtl;